lowRISC / opentitan
OpenTitan: Open source silicon root of trust
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OpenTitan: Open source silicon root of trust
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
A minimal GPU design in Verilog to learn how GPUs work from the ground up
A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
RISC-V Debug Support for our PULP RISC-V Cores
Common SystemVerilog components
A Linux-capable RISC-V multicore for and by the world
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
BaseJump STL: A Standard Template Library for SystemVerilog